Hiring Now: Cellular SOC Design Verification Engineer - Entry

Key Job Details:

• Compensation: a competitive salary
• Company: Workwarp
• Position: Cellular SOC Design Verification Engineer - Entry Level - reputed company
• Location: Remote
• Start Date: Immediate openings available

 

 

reputed company is hiring Cellular SOC Design Verification Engineer - Entry Level Do you have a passion for invention and self-challenge? This position gives you an opportunity to be a part of one of the most cutting edge and key projects that reputed company’s Silicon Engineering Group has embarked upon to-date. As a Design Verification Engineer on reputed company, you'll be at the center of the verification effort... reputed company our silicon design group responsible for crafting and productizing state-of-the-art Cellular SoCs! You will have the opportunity to contribute to the verification effort of a set of reputed company SOCs delivering the Cellular solution. You will integrate multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM based test bench, implement effective coverage driven and directed test suites, deploy new tools and methodologies to deliver chips that are right-first-time. By collaborating with other product development groups across reputed company, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! Description Through this experience, you will learn reputed company aspects of a large scale SOC design, reputed company verification test benches, different types of SOC architectures, multiple high speed protocols, industry-standard low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Cellular protocol, FW- HW interactions, complexities of multi-chip SOC debug architecture, etc. Key Qualifications • MS in EE or CS. Coursework in Digital Design, Computer Architecture, Object Oriented Programming, Networking Protocol. Programming experience in SystemVerilog or Python or C++ or Java. • Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges. • BS and a minimum of 3 years of relevant industry experience is required. Education & Experience BSEE required. • MSEE or beyond is preferred Apply Job!

 

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